How to...

Install the toolchain

  1. Install Python 2.7

Warning

Windows users: DON’T FORGET to select Add python.exe to Path feature on the “Customize” stage.

  1. Connect to the internet
  2. Launch the toolchain installation process
Go to Tools > Install toolchain. Be patient for the toolchain installation.

Note

When the toolchain is installed, the menu option appears as Tools > Upgrade toolchain

Install the drivers

  1. Install the toolchain (required for Windows)
  2. Enable the FTDI drivers
Go to Tools > Enable drivers. Each OS has a different process. This configuration requires administration privileges.

Note

To revert the drivers configuration go to Tools > Disable drivers

Create a project

  1. Create a new project

    Go to Edit > New project, write your project’s name and press OK.

    ../_images/new.png

  1. Add your blocks
  1. Code blocks

    Click on Basic > Code, add the code ports. Input and output ports are separated by a space. Port names are separated by a comma. E.g.: a,b c.

    This block contains a text editor to write your module verilog code. Module header and footer are not required.

    ../_images/code.png

  1. Info blocks

    Click on Basic > Info.

    This block contains a text editor to add comments about the project.

    ../_images/info.png

  1. Input/Output blocks

    Click on Basic > Input or Basic > Output, write the block’s name and press OK.

    These blocks contain a FPGA pin selector depending on the selected board.

    ../_images/io.png

  1. Bit blocks

    Click on Bit > 0 or Bit > 1.

    These blocks are low and high logic drivers.

    ../_images/bit.png

  1. Config block

    Click on Config > Pull up or Config > Pull up inv.

    This block must be connected to input ports in order to configure a pull up.

    ../_images/config.png

  1. Logic blocks

    Go to the Logic menu and select. This menu contains Logic Gates, Combinational blocks and Sequential flip-flops.

    ../_images/logic.png

  1. Connect your blocks
../_images/bwire.png

../_images/wire.png

  1. Select your board

    Go to Boards menu and select Go board, iCE40-HX8K, iCEstick, Icezum Alhambra or icoBOARD 1.0.

    ../_images/board.png

  1. Set FPGA I/O pins

    Select all Input/Output blocks’ pins.

    ../_images/fpgapin.png

  1. Save the project

    Go to Edit > Save:

    It will be saved as an .ice file.

    ../_images/save.png

Upload a bitstream

  1. Open a project

    Go to Edit > Open project and select an .ice file.


  2. Verify the project

    Go to Tools > Verify.

    This option checks the generated verilog code using apio verify.

    ../_images/verify.png

  3. Build the project

    Go to Tools > Build.

    This option generates a bitstream using apio build.

    ../_images/build.png

  4. Upload the project

    Connect your FPGA board and press Tools > Upload. This option uses apio upload.

    ../_images/upload.png

Note

If the FPGA toolchain is not installed, it will be installed automatically when any tool is pressed. It can also be installed or removed in the menu Tools section.

../_images/installtoolchain.png

Create a block

  1. Open a project

    Go to Edit > Open project and select an .ice file.


../_images/project.png
  1. Verify the project

    Go to Tools > Verify.


  1. Export the project as a block

    Go to Edit > Export as block.

    It will be saved as an .iceb file.

    ../_images/export.png

Note

Input/Output blocks will become new Block I/O pins.

Use a custom block

  1. Open or create a new project

  1. Import the custom block

    Go to Edit > Import block and select an .iceb file.

    ../_images/import.png

    ../_images/customblock.png

  2. Examine the custom block

    Complex blocks can be examined by double clicking the block.

    ../_images/examine.png

Include a list file

If your code block contains a list file(s), for example:

$readmemh("rom.list", rom);
  1. Save the ice project
  2. Copy the list file(s) in the project directory
  3. Build and upload the project

Include a verilog (header) file

If your code block includes a verilog (header) file(s), for example:

// @include lib.vh
// @include math.v

`include "lib.vh"
  1. Save the ice project
  2. Copy the verilog (header) file(s) in the project’s directory
  3. Build and upload the project

Configure a remote host

I you want to use a RPi, eg pi@192.168.0.22, or another computer from Icestudio as a client, first configure the host:

  1. Copy your SSH public key into the server
$ ssh-keygen
$ ssh-copy-id -i .ssh/id_rsa.pub pi@192.168.0.22
  1. Install apio in the server
$ ssh pi@192.168.0.22
$ sudo pip install -U apio
$ apio install --all
$ apio drivers --enable  # For FTDI devices
  1. Enter the host name in Icestudio, Edit > Remote hostname

    ../_images/remotehost.png

  2. Now, Verify, Build and Upload tools will run in the selected host