Compiler

The JSON structure of a project is a block definition.

Output verilog structure:

  1. Modules
  2. Main module
    1. Wires definition
    2. Wires connections
    3. Blocks instances

Implementation

Show/Hide code

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/**
 * @author Jesús Arroyo Torrens <jesus.jkhlg@gmail.com>
 *
 * June 2016
 */

 'use strict';

var fs = require('fs');
var sha1 = require('sha1');


function digestId(id, force) {
  if (id.indexOf('-') != -1) {
    return 'v' + sha1(id).toString().substring(0, 6);
  }
  else {
    return id.replace('.', '_');
  }
}

function module(data) {
  var code = '';

  if (data &&
      data.name &&
      data.ports &&
      data.content) {

    // Header

    code += 'module ';
    code += data.name;
    code += ' (';

    var params = [];
    var paramsSpace = 10 + data.name.length;

    for (var i in data.ports.in) {
      params.push('input ' + data.ports.in[i]);
    }
    for (var o in data.ports.out) {
      params.push('output ' + data.ports.out[o]);
    }

    code += params.join(',\n' + new Array(paramsSpace).join(' '));

    code += ');\n';

    // Content

    var content = data.content.split('\n');

    content.forEach(function (element, index, array) {
      array[index] = ' ' + element;
    });

    code += content.join('\n');

    // Footer

    code += '\nendmodule\n\n';
  }

  return code;
}

function getPorts(project) {
  var ports = {
    in: [],
    out: []
  };
  var graph = project.graph;

  for (var i in graph.blocks) {
    var block = graph.blocks[i];
    if (block.type == 'basic.input') {
      ports.in.push(digestId(block.id));
    }
    else if (block.type == 'basic.output') {
      ports.out.push(digestId(block.id));
    }
  }

  return ports;
}

function getContent(name, project) {
  var content = '';
  var graph = project.graph;

  // Wires

  for (var w in graph.wires) {
    content += 'wire w' + w + ';\n'
  }

  // I/O connections

  for (var w in graph.wires) {
    var wire = graph.wires[w];
    for (var i in graph.blocks) {
      var block = graph.blocks[i];
      if (block.type == 'basic.input') {
        if (wire.source.block == block.id) {
          content += 'assign w' + w + ' = ' + digestId(block.id) + ';\n';
        }
      }
      else if (block.type == 'basic.output') {
        if (wire.target.block == block.id) {
          content += 'assign ' + digestId(block.id) + ' = w' + w + ';\n';
        }
      }
    }
  }

  // Wires Connections

  var numWires = graph.wires.length;
  for (var i = 1; i < numWires; i++) {
    for (var j = 0; j < i; j++) {
      var wi = graph.wires[i];
      var wj = graph.wires[j];
      if (wi.source.block == wj.source.block &&
          wi.source.port == wj.source.port) {
        content += 'assign w' + i + ' = w' + j + ';\n';
      }
    }
  }

  // Block instances

  var instances = []
  for (var b in graph.blocks) {
    var block = graph.blocks[b];
    if (block.type != 'basic.input' &&
        block.type != 'basic.output' &&
        block.type != 'basic.info') {

      var id = digestId(block.type, true);
      if (block.type == 'basic.code') {
        id += '_' + digestId(block.id);
      }
      instances.push(name + '_' + digestId(id) + ' ' + digestId(block.id) + ' (');

      // Parameters

      var params = [];
      var paramsNames = [];
      for (var w in graph.wires) {
        var param = '';
        var paramName = '';
        var wire = graph.wires[w];
        if (block.id == wire.source.block) {
          paramName = digestId(wire.source.port);
        }
        else if (block.id == wire.target.block) {
          paramName = digestId(wire.target.port);
        }
        if (paramName && paramsNames.indexOf(paramName) == -1) {
          paramsNames.push(paramName);
          param += ' .' + paramName;
          param += '(w' + w + ')';
          params.push(param);
        }
      }

      instances.push(params.join(',\n') + '\n);');
    }
  }
  content += instances.join('\n');

  return content;
}

function verilogCompiler(name, project) {
  var code = '';

  if (project &&
      project.graph) {

    // Scape dot in name

    name = digestId(name);

    // Main module

    if (name) {
      var data = {
        name: name,
        ports: getPorts(project),
        content: getContent(name, project)
      };
      code += module(data);
    }

    // Dependencies modules

    for (var d in project.deps) {
      code += verilogCompiler(name + '_' + digestId(d, true), project.deps[d]);
    }

    // Code modules

    for (var i in project.graph.blocks) {
      var block = project.graph.blocks[i];
      if (block) {
        if (block.type == 'basic.code') {
          var data = {
            name: name + '_' + digestId(block.type, true) + '_' + digestId(block.id),
            ports: block.data.ports,
            content: block.data.code
          }
          code += module(data);
        }
      }
    }
  }

  return code;
}

function pcfCompiler(project) {
  var code = '';

  for (var i in project.graph.blocks) {
    var block = project.graph.blocks[i];
    if (block.type == 'basic.input' ||
        block.type == 'basic.output') {
      code += 'set_io ';
      code += digestId(block.id);
      code += ' ';
      code += block.data.pin.value;
      code += '\n';
    }
  }

  return code;
}

// Examples

var fs = require('fs');

function compare_string(s1, s2) {
  var diff = [];
  var string1 = s1.split(" ");
  var string2 = s2.split(" ");
  var size = Math.max(s1.length, s2.length);

  for(var x = 0; x < size; x++) {
    if(string1[x] != string2[x]) {
      diff.push(string1[x]);
    }
  }

  return diff.join(' ');
}

function test_example(name, extension) {
  var filename = ['..', 'resources', 'examples', name, name].join('/');
  fs.readFile(filename + '.' + extension, 'utf8', function (err, data) {
    if (err) throw err;

    var example = JSON.parse(fs.readFileSync(filename + '.ice'));
    if (extension == 'v') {
      var s1 = verilogCompiler('main', example).replace(/[\r\n]/g, "");
    }
    else {
      var s1 = pcfCompiler(example).replace(/[\r\n]/g, "");
    }
    var s2 = data.replace(/[\r\n]/g, "");

    if (extension == 'v') {
      process.stdout.write('Testing ' + name + ' v   ...');
    }
    else {
      process.stdout.write('Testing ' + name + ' pcf ...');
    }
    if (s1 == s2) {
      process.stdout.write(' [OK]\n');
    }
    else {
      process.stdout.write(' [Fail]\n');
      process.stdout.write(compare_string(s1, s2) + '\n');
    }
  });
}

// Test examples

test_example('low', 'v');
test_example('low', 'pcf');
test_example('not', 'v');
test_example('not', 'pcf');
test_example('or', 'v');
test_example('or', 'pcf');
test_example('cnot', 'v');
test_example('cnot', 'pcf');
test_example('dnot', 'v');
test_example('dnot', 'pcf');

//console.log(verilogCompiler('main', JSON.parse(fs.readFileSync('../resources/examples/dnot/dnot.ice'))));
//console.log(pcfCompiler(JSON.parse(fs.readFileSync('../resources/examples/dnot/dnot.ice'))));

npm install fs sha1
node compiler.js

Examples

Low project

../_images/low-project.png

File: low.ice

Show/Hide code

{
  "board": "icezum",
  "graph": {
    "blocks": [
      {
        "id": "b959fb96-ac67-4aea-90b3-ed35a4c17bf5",
        "type": "basic.code",
        "data": {
          "code": "// Bit 0\n\nassign v = 1'b0;",
          "ports": {
            "in": [],
            "out": [
              "v"
            ]
          }
        },
        "position": {
          "x": 96,
          "y": 96
        }
      },
      {
        "id": "19c8f68d-5022-487f-9ab0-f0a3cd58bead",
        "type": "basic.output",
        "data": {
          "label": "o",
          "pin": {
            "name": "LED0",
            "value": "95"
          }
        },
        "position": {
          "x": 608,
          "y": 192
        }
      }
    ],
    "wires": [
      {
        "source": {
          "block": "b959fb96-ac67-4aea-90b3-ed35a4c17bf5",
          "port": "v"
        },
        "target": {
          "block": "19c8f68d-5022-487f-9ab0-f0a3cd58bead",
          "port": "in"
        }
      }
    ]
  },
  "deps": {},
  "image": "",
  "state": {
    "pan": {
      "x": 0,
      "y": 0
    },
    "zoom": 1
  }
}

Generates

module main (output v608bd9);
 wire w0;
 assign v608bd9 = w0;
 main_basic_code_v68c173 v68c173 (
  .v(w0)
 );
endmodule

module main_basic_code_v68c173 (output v);
 // Bit 0
 
 assign v = 1'b0;
endmodule
set_io v608bd9 95

Not project

../_images/not-project.png

File: not.ice

Show/Hide code

{
  "board": "icezum",
  "graph": {
    "blocks": [
      {
        "id": "18c2ebc7-5152-439c-9b3f-851c59bac834",
        "type": "basic.input",
        "data": {
          "label": "x",
          "pin": {
            "name": "SW1",
            "value": "10"
          }
        },
        "position": {
          "x": 64,
          "y": 144
        }
      },
      {
        "id": "664caf9e-5f40-4df4-800a-b626af702e62",
        "type": "basic.output",
        "data": {
          "label": "y",
          "pin": {
            "name": "LED0",
            "value": "95"
          }
        },
        "position": {
          "x": 752,
          "y": 144
        }
      },
      {
        "id": "5365ed8c-e5db-4445-938f-8d689830ea5c",
        "type": "basic.code",
        "data": {
          "code": "// NOT logic gate\n\nassign c = ! a;",
          "ports": {
            "in": [
              "a"
            ],
            "out": [
              "c"
            ]
          }
        },
        "position": {
          "x": 256,
          "y": 48
        }
      }
    ],
    "wires": [
      {
        "source": {
          "block": "18c2ebc7-5152-439c-9b3f-851c59bac834",
          "port": "out"
        },
        "target": {
          "block": "5365ed8c-e5db-4445-938f-8d689830ea5c",
          "port": "a"
        }
      },
      {
        "source": {
          "block": "5365ed8c-e5db-4445-938f-8d689830ea5c",
          "port": "c"
        },
        "target": {
          "block": "664caf9e-5f40-4df4-800a-b626af702e62",
          "port": "in"
        }
      }
    ]
  },
  "deps": {},
  "image": "",
  "state": {
    "pan": {
      "x": 0,
      "y": 0
    },
    "zoom": 1
  }
}

Generates

module main (input v0e28cb,
             output vcbab45);
 wire w0;
 wire w1;
 assign w0 = v0e28cb;
 assign vcbab45 = w1;
 main_basic_code_vd54ca1 vd54ca1 (
  .a(w0),
  .c(w1)
 );
endmodule

module main_basic_code_vd54ca1 (input a,
                                output c);
 // NOT logic gate
 
 assign c = ! a;
endmodule
set_io v0e28cb 10
set_io vcbab45 95

Or project

../_images/or-project.png

File: or.ice

Show/Hide code

{
  "board": "icezum",
  "graph": {
    "blocks": [
      {
        "id": "18c2ebc7-5152-439c-9b3f-851c59bac834",
        "type": "basic.input",
        "data": {
          "label": "x",
          "pin": {
            "name": "SW1",
            "value": "10"
          }
        },
        "position": {
          "x": 64,
          "y": 80
        }
      },
      {
        "id": "97b51945-d716-4b6c-9db9-970d08541249",
        "type": "basic.input",
        "data": {
          "label": "y",
          "pin": {
            "name": "SW2",
            "value": "11"
          }
        },
        "position": {
          "x": 64,
          "y": 208
        }
      },
      {
        "id": "664caf9e-5f40-4df4-800a-b626af702e62",
        "type": "basic.output",
        "data": {
          "label": "o",
          "pin": {
            "name": "LED0",
            "value": "95"
          }
        },
        "position": {
          "x": 752,
          "y": 144
        }
      },
      {
        "id": "00925b04-5004-4307-a737-fa4e97c8b6ab",
        "type": "basic.code",
        "data": {
          "code": "// OR logic gate\n\nassign c = a | b;",
          "ports": {
            "in": [
              "a",
              "b"
            ],
            "out": [
              "c"
            ]
          }
        },
        "position": {
          "x": 256,
          "y": 48
        }
      }
    ],
    "wires": [
      {
        "source": {
          "block": "18c2ebc7-5152-439c-9b3f-851c59bac834",
          "port": "out"
        },
        "target": {
          "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
          "port": "a"
        }
      },
      {
        "source": {
          "block": "97b51945-d716-4b6c-9db9-970d08541249",
          "port": "out"
        },
        "target": {
          "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
          "port": "b"
        }
      },
      {
        "source": {
          "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
          "port": "c"
        },
        "target": {
          "block": "664caf9e-5f40-4df4-800a-b626af702e62",
          "port": "in"
        }
      }
    ]
  },
  "deps": {},
  "image": "",
  "state": {
    "pan": {
      "x": 0,
      "y": 0
    },
    "zoom": 1
  }
}

Generates

module main (input v0e28cb,
             input v3ca442,
             output vcbab45);
 wire w0;
 wire w1;
 wire w2;
 assign w0 = v0e28cb;
 assign w1 = v3ca442;
 assign vcbab45 = w2;
 main_basic_code_vf4938a vf4938a (
  .a(w0),
  .b(w1),
  .c(w2)
 );
endmodule

module main_basic_code_vf4938a (input a,
                                input b,
                                output c);
 // OR logic gate
 
 assign c = a | b;
endmodule
set_io v0e28cb 10
set_io v3ca442 11
set_io vcbab45 95

Cnot project

../_images/cnot-project.png

File: cnot.ice

Show/Hide code

{
  "image": "",
  "state": {
    "pan": {
      "x": 0,
      "y": 0
    },
    "zoom": 1
  },
  "board": "icezum",
  "graph": {
    "blocks": [
      {
        "id": "db6b84db-bc29-46d6-86a4-f48cc50c8076",
        "type": "not",
        "data": {},
        "position": {
          "x": 280,
          "y": 248
        }
      },
      {
        "id": "ba7c5fb1-172d-4fa0-8a59-1905c4a71332",
        "type": "or",
        "data": {},
        "position": {
          "x": 464,
          "y": 136
        }
      },
      {
        "id": "55c6c056-3630-4482-ad47-f4d9ee83b835",
        "type": "basic.input",
        "data": {
          "label": "a",
          "pin": {
            "name": "SW1",
            "value": "10"
          }
        },
        "position": {
          "x": 88,
          "y": 248
        }
      },
      {
        "id": "c8c6eed3-548c-49c7-a162-282179d427b1",
        "type": "basic.output",
        "data": {
          "label": "b",
          "pin": {
            "name": "LED0",
            "value": "95"
          }
        },
        "position": {
          "x": 640,
          "y": 136
        }
      },
      {
        "id": "d2a2eac1-f8b0-4e5b-a693-626f6d14b8e5",
        "type": "low",
        "data": {},
        "position": {
          "x": 280,
          "y": 120
        }
      }
    ],
    "wires": [
      {
        "source": {
          "block": "d2a2eac1-f8b0-4e5b-a693-626f6d14b8e5",
          "port": "19c8f68d-5022-487f-9ab0-f0a3cd58bead"
        },
        "target": {
          "block": "ba7c5fb1-172d-4fa0-8a59-1905c4a71332",
          "port": "18c2ebc7-5152-439c-9b3f-851c59bac834"
        }
      },
      {
        "source": {
          "block": "55c6c056-3630-4482-ad47-f4d9ee83b835",
          "port": "out"
        },
        "target": {
          "block": "db6b84db-bc29-46d6-86a4-f48cc50c8076",
          "port": "18c2ebc7-5152-439c-9b3f-851c59bac834"
        }
      },
      {
        "source": {
          "block": "db6b84db-bc29-46d6-86a4-f48cc50c8076",
          "port": "664caf9e-5f40-4df4-800a-b626af702e62"
        },
        "target": {
          "block": "ba7c5fb1-172d-4fa0-8a59-1905c4a71332",
          "port": "97b51945-d716-4b6c-9db9-970d08541249"
        }
      },
      {
        "source": {
          "block": "ba7c5fb1-172d-4fa0-8a59-1905c4a71332",
          "port": "664caf9e-5f40-4df4-800a-b626af702e62"
        },
        "target": {
          "block": "c8c6eed3-548c-49c7-a162-282179d427b1",
          "port": "in"
        }
      }
    ]
  },
  "deps": {
    "or": {
      "graph": {
        "blocks": [
          {
            "id": "18c2ebc7-5152-439c-9b3f-851c59bac834",
            "type": "basic.input",
            "data": {
              "label": "x"
            },
            "position": {
              "x": 64,
              "y": 80
            }
          },
          {
            "id": "97b51945-d716-4b6c-9db9-970d08541249",
            "type": "basic.input",
            "data": {
              "label": "y"
            },
            "position": {
              "x": 64,
              "y": 208
            }
          },
          {
            "id": "664caf9e-5f40-4df4-800a-b626af702e62",
            "type": "basic.output",
            "data": {
              "label": "o"
            },
            "position": {
              "x": 752,
              "y": 144
            }
          },
          {
            "id": "00925b04-5004-4307-a737-fa4e97c8b6ab",
            "type": "basic.code",
            "data": {
              "code": "// OR logic gate\n\nassign c = a | b;",
              "ports": {
                "in": [
                  "a",
                  "b"
                ],
                "out": [
                  "c"
                ]
              }
            },
            "position": {
              "x": 256,
              "y": 48
            }
          }
        ],
        "wires": [
          {
            "source": {
              "block": "18c2ebc7-5152-439c-9b3f-851c59bac834",
              "port": "out"
            },
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Generates

module main (input va1d1bb,
             output vecf2e3);
 wire w0;
 wire w1;
 wire w2;
 wire w3;
 assign w1 = va1d1bb;
 assign vecf2e3 = w3;
 main_not va44cd3 (
  .v0e28cb(w1),
  .vcbab45(w2)
 );
 main_or v0b7a71 (
  .v0e28cb(w0),
  .v3ca442(w2),
  .vcbab45(w3)
 );
 main_low v2d7478 (
  .v608bd9(w0)
 );
endmodule

module main_or (input v0e28cb,
                input v3ca442,
                output vcbab45);
 wire w0;
 wire w1;
 wire w2;
 assign w0 = v0e28cb;
 assign w1 = v3ca442;
 assign vcbab45 = w2;
 main_or_basic_code_vf4938a vf4938a (
  .a(w0),
  .b(w1),
  .c(w2)
 );
endmodule

module main_or_basic_code_vf4938a (input a,
                                   input b,
                                   output c);
 // OR logic gate
 
 assign c = a | b;
endmodule

module main_not (input v0e28cb,
                 output vcbab45);
 wire w0;
 wire w1;
 assign w0 = v0e28cb;
 assign vcbab45 = w1;
 main_not_basic_code_vd54ca1 vd54ca1 (
  .a(w0),
  .c(w1)
 );
endmodule

module main_not_basic_code_vd54ca1 (input a,
                                    output c);
 // NOT logic gate
 
 assign c = ! a;
endmodule

module main_low (output v608bd9);
 wire w0;
 assign v608bd9 = w0;
 main_low_basic_code_v68c173 v68c173 (
  .v(w0)
 );
endmodule

module main_low_basic_code_v68c173 (output v);
 // Bit 0
 
 assign v = 1'b0;
endmodule
set_io va1d1bb 10
set_io vecf2e3 95

Dnot project

../_images/dnot-project.png

File: dnot.ice

Show/Hide code

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Generates

module main (input v121a14,
             output v31c150,
             output v71e6a9);
 wire w0;
 wire w1;
 wire w2;
 wire w3;
 assign w0 = v121a14;
 assign w1 = v121a14;
 assign v31c150 = w2;
 assign v71e6a9 = w3;
 assign w1 = w0;
 main_cnot vc6f497 (
  .va1d1bb(w1),
  .vecf2e3(w3)
 );
 main_not v59fef8 (
  .v0e28cb(w0),
  .vcbab45(w2)
 );
endmodule

module main_logic_not (input v0e28cb,
                       output vcbab45);
 wire w0;
 wire w1;
 assign w0 = v0e28cb;
 assign vcbab45 = w1;
 main_logic_not_basic_code_vd54ca1 vd54ca1 (
  .a(w0),
  .c(w1)
 );
endmodule

module main_logic_not_basic_code_vd54ca1 (input a,
                                          output c);
 // NOT logic gate
 
 assign c = ~ a;
endmodule

module main_cnot (input va1d1bb,
                  output vecf2e3);
 wire w0;
 wire w1;
 wire w2;
 wire w3;
 assign w1 = va1d1bb;
 assign vecf2e3 = w3;
 main_cnot_not va44cd3 (
  .v0e28cb(w1),
  .vcbab45(w2)
 );
 main_cnot_or v0b7a71 (
  .v0e28cb(w0),
  .v3ca442(w2),
  .vcbab45(w3)
 );
 main_cnot_low v2d7478 (
  .v608bd9(w0)
 );
endmodule

module main_cnot_or (input v0e28cb,
                     input v3ca442,
                     output vcbab45);
 wire w0;
 wire w1;
 wire w2;
 assign w0 = v0e28cb;
 assign w1 = v3ca442;
 assign vcbab45 = w2;
 main_cnot_or_basic_code_vf4938a vf4938a (
  .a(w0),
  .b(w1),
  .c(w2)
 );
endmodule

module main_cnot_or_basic_code_vf4938a (input a,
                                        input b,
                                        output c);
 // OR logic gate
 
 assign c = a | b;
endmodule

module main_cnot_not (input v0e28cb,
                      output vcbab45);
 wire w0;
 wire w1;
 assign w0 = v0e28cb;
 assign vcbab45 = w1;
 main_cnot_not_basic_code_vd54ca1 vd54ca1 (
  .a(w0),
  .c(w1)
 );
endmodule

module main_cnot_not_basic_code_vd54ca1 (input a,
                                         output c);
 // NOT logic gate
 
 assign c = ! a;
endmodule

module main_cnot_low (output v608bd9);
 wire w0;
 assign v608bd9 = w0;
 main_cnot_low_basic_code_v68c173 v68c173 (
  .v(w0)
 );
endmodule

module main_cnot_low_basic_code_v68c173 (output v);
 // Bit 0
 
 assign v = 1'b0;
endmodule

module main_not (input v0e28cb,
                 output vcbab45);
 wire w0;
 wire w1;
 assign w0 = v0e28cb;
 assign vcbab45 = w1;
 main_not_basic_code_vd54ca1 vd54ca1 (
  .a(w0),
  .c(w1)
 );
endmodule

module main_not_basic_code_vd54ca1 (input a,
                                    output c);
 // NOT logic gate
 
 assign c = ! a;
endmodule
set_io v121a14 10
set_io v31c150 95
set_io v71e6a9 96